The present invention relates to a circuit for driving a modularized memory.
In en electronic calculator such as a personal computer, etc., it has been generally proposed to include modularized memory. The modularized memory is, as illustrated in, e.g., FIG. 10, packaged with a plurality of memory modules and also packaged with a memory controller MC for driving these memory modules. The modularized memory is constructed by connecting the memory controller MC to the memory modules through connectors.
Each memory module is constructed by connecting dynamic RAMs (DRAMs) through a wire pattern, and therefore, if packaged with the plurality of memory modules, the wires within the memory modules take a stubby shape (branch wiring).
The number of DRAMs packaged in the memory module differs depending on a capacity of each DRAM. For instance, in the case of constructing an 8 Mbit memory module by use of 16 Mbyte DRAMs, the number of the DRAMs packaged in the memory module is 4. Further, in the case of constructing the 8 Mbyte memory module by use of 4 Mbit DRAMs, the number of the DRAMs packaged in the memory module is 16. Thus, the capacity of the memory module differs depending on the capacity and the number of the DRAMs packaged therein.
When writing data to the above-described memory circuit, the memory controller MC accumulates electric charge in a capacitor (an electrostatic capacity element) constituting the DRAM to discharge the capacitor. On the other hand, when reading the data from the memory circuit, the memory controller MC refers to whether or not there exists an electric charge accumulated in the capacitor (the electric charge being therein: "1", and no electric charge being therein: "0"),
In the prior art memory drive circuit described above, there might be a stubby wire arrangement in the memory module, and hence the wire impedance is mismatched. When the memory controller MC transmits a signal to the memory module, the signal is reflected due to the mismatching of the impedance. The reflected signal (hereinafter referred to as a refection noise) runs through the wire connecting the memory module to the memory controller and is then overlapped with the signal from the memory controller MC.
In this case, the signal transmitted from the memory controller to the memory module may be any of several signals. This transmitted signal may be a write enable signal (WE) assuming a high level (H) when effecting a read process from the memory module and assuming a low level (L) when effecting a write process thereto. The transmitted signal may be a row address strobe (RAS) showing a row address specifying timing of the DRAM constructed of capacitors arrayed in matrix the transmitted signal may be a column address strobe (CAS) indicating a column address specifying timing of the DRAM, and an address signal.
The write enable signal WE, the row address strobe signal RAS, the column address strobe signal CAS and the address signal are defined as edge trigger signals using a point-of-variation of the signal value. Therefore, if these signals are overlapped with the reflection noises, there occurs be a split portion and a stepped portion in the waveform of the signal, resulting in a malfunction of the DRAM.
Further, the reflection noises enlarge as the load capacity of the memory module increases. Therefore, if packaged with the memory modules having different capacities, as in an example of, e.g., FIG. 10, the load capacity of a memory module B is larger than that of a memory module A. Hence, the reflection noises caused in the memory module B are larger than the reflection noises produced in the memory module A. The reflection noises produced in the memory module B might therefore influence even the memory elements of the memory module A.
Moreover, when extending the memory modules, the load capacity of the whole memory circuit increases. Consequently a rising time and a falling time of the signal outputted from the memory controller MC must be elongated, with the result that a timing error occurs due to a longer delay. A method of preventing such a timing error may be a method of enhancing the driving capability of the memory controller. If the number of packaged memory modules is small, however, an overshoot or a undershoot is caused, resulting in a malfunction of the DRAM.